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Portfolio Alexandre Kiss

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research · Fall 2025

MoS₂ floating-gate memory

A monolayer MoS₂ transistor with a buried platinum floating gate, studied as a non-volatile memory and a programmable resistance.

Summary view

Project details

  1. source drain MoS₂, one layer HfO₂ floating gate · Pt gate program + erase − stored charge

    Charge storage in a floating gate

    A floating-gate transistor stores charge in a metal gate surrounded by insulator and electrically isolated from the contacts. The stored charge shifts the voltage at which the transistor turns on. Reading that threshold provides a memory state that can persist after the external programming voltage is removed.

  2. from above nearby charge one layer Mo S

    A monolayer MoS₂ channel

    Molybdenum disulphide retains a band gap in a single layer and provides a thin channel whose conductance is sensitive to nearby charge. The lab project examined two uses of this device: storing distinct memory states through a threshold shift, and setting its conductance as a programmable resistance.

  3. gate HfO₂ floating gate HfO₂ MoS₂ monolayer Ti–Au contacts

    Cleanroom fabrication at CMi

    Our three-person team fabricated the device at EPFL’s CMi cleanroom, using hafnium oxide insulation, a buried platinum floating gate and monolayer MoS₂. Oxygen-plasma patterning defined the channel, followed by titanium–gold contacts. I took part in both the fabrication and the electrical characterisation.

  4. Electrical measurement setup

    The chip was mounted in a zero-insertion-force socket inside a light-shielded breakout box and connected by triaxial cables to a source-measure unit with femtoampere resolution. With the drain held at 100 mV, the gate was swept from −10 V to +10 V and back. Thresholds were read at a fixed current reference.

  5. −100+10 gate voltage, V drain current, log reference current 0.8 V 6.2 V forward sweep reverse sweep 5.4 V window measured thresholds; schematic curves

    Measured memory window

    5.4 V between thresholds of 0.8 V and 6.2 V

    The forward and reverse gate sweeps gave thresholds of 0.8 V and 6.2 V, a 5.4 V memory window consistent with charge stored in the floating gate. Published devices reach 10.6 V when swept to ±12.5 V. Our sweep stopped at ±10 V; sweep speed and oxide quality also affect this comparison.

  6. programming voltage −10 4 6 8 10 0.293 µS · 4 V0.080 µS · 6 Vabout 0 · 8, 10 V read: drain ±0.5 V

    Programming the channel conductance

    After erasing at −10 V, sweeps to 4, 6, 8 and 10 V programmed different states. A small drain sweep gave 0.293 µS after 4 V, 0.080 µS after 6 V and nearly zero after 8 V. The intermediate states were less stable than published examples, suggesting incremental programming with verification as a useful next test.

The packaged MoS₂ memory chip, its die wire-bonded, seated in a zero-insertion-force socket on a measurement board.
Packaged MoS₂ chip in a zero-insertion-force socket on the measurement board, connected to a source-measure unit.

My contribution

As part of a three-person team, I fabricated and characterised a MoS₂ floating-gate transistor, measuring its memory window and programmable conductance.